1. Field of the Invention
The present invention relates to methods of manufacturing a silicon carbide semiconductor device.
2. Description of the Prior Art
Silicon carbide (SiC) allows for manufacturing a silicon carbide semiconductor device that has a higher breakdown voltage characteristic compared to using conventional silicon (Si), and has been expected as a material for a high power semiconductor device of the next generation. In manufacturing a silicon carbide semiconductor device from such silicon carbide, in order to control its conductivity-type and conductivity, an n-type or a p-type impurity is ion-implanted into a silicon carbide wafer that consists of silicon carbide layers formed by epitaxial crystal growth on a silicon carbide substrate. After the ion implantation, in order to activate the implanted ion and remove crystal defects having been created owing to the ion implantation, the silicon carbide wafer is processed by an annealing treatment in which the wafer is exposed to a hot atmosphere of an inert gas such as argon (Ar). Such annealing treatment of a silicon carbide wafer is preferably performed at a temperature as high as possible, in most cases at above 1500° C., desirably at above 1600° C., for stabilizing the characteristic thereof.
Annealing a silicon carbide wafer at such a high temperature, however, creates asperity called step bunching on the surface of the silicon carbide wafer. The reason for the creation of step bunching is as follows.
A silicon carbide wafer is typically obtained by forming silicon carbide layers by epitaxial crystal growth on a silicon carbide substrate. The epitaxial crystal growth is performed in such a way that the crystal axis is inclined approximately four or eight degrees with respect to the C-axis that is orthogonal to the (0001) crystal plane, in order to prevent crystals of, for example, the 6H- and 4H-types from mixedly growing on the same crystal surface.
When the silicon carbide wafer thus crystallized with its crystal axis being inclined is exposed to such a high temperature as in annealing treatments, silicon (Si) and carbon (C), which are the constituent elements thereof, evaporate from the surface of the silicon carbide wafer. In the evaporation, since silicon and carbon have different evaporating conditions and the crystal axis is inclined, the evaporation rates of silicon and carbon differ from each other in the surface of the silicon carbide wafer. As a result, step bunching is created on the silicon carbide wafer surface.
The step bunching thus created becomes an obstacle in forming a gate oxide film on the silicon carbide wafer having been annealed and further becomes an obstacle in forming a gate electrode on the gate oxide film. For example, there is a possibility of contactability reducing and of the leakage characteristic deteriorating due to asperity in the boundary surfaces between the silicon carbide wafer and the gate oxide film, or the gate oxide film and the gate electrode.
For that reason, to prevent or reduce step bunching has been a major problem for quality stability of silicon carbide semiconductor devices and for improvement in their manufacturing yields.
As for a method of preventing or reducing such step bunching, a technology has been disclosed in, for example, Patent Document 1 (Japanese Patent No. 3760688) in which a diamond-like carbon film or an organic film is formed on the surface of a silicon carbide wafer as a protection film that prevents evaporation of silicon and carbon during an annealing treatment.
Another technology has been disclosed in Patent Document 2 (Japanese Patent Application Publication No. 2005-353771) in which a carbon film is formed on an ion-implanted side of a silicon carbide wafer by a sputtering method as a protection film that prevents evaporation of silicon and carbon during an annealing treatment.
In the method of Patent Document 1, however, a carbonized resist is used as a protection film. A resist generally includes numbers of elements other than carbon and hydrogen for enhancing its optical activity and contactability. These elements other than carbon and hydrogen remain behind as contaminants in the protection film formed from the carbonized resist. For that reason, the contaminants evaporate or scatter during an annealing treatment, to be a source of contamination to the silicon carbide semiconductor device.
Moreover, in the method of Patent Document 2, while a carbon film formed by a sputtering method is used as a protection film, a sputtering method also sputters part of materials (for example, metal materials such as aluminum and stainless steel) that make up the sputtering apparatus. Accordingly, these sputtered materials scatter as contaminants, to be a source of contamination to the silicon carbide semiconductor device.
Furthermore, in the methods of Patent Documents 1 and 2, a protection film is formed on one surface of a silicon carbide wafer, to be more specific, on a side that is ion-implanted with an impurity, of the silicon carbide wafer. When a protection film is thus formed on only one surface of a silicon carbide wafer, unbalanced thermal stress is created in the silicon carbide wafer during an annealing treatment due to a temperature gradient produced therein and difference between the thermal expansion coefficients of the silicon carbide wafer and the protection film, which results in an increase of crystal defects in the silicon carbide wafer.
Such ingress of contaminants and increase of crystal defects are factors that contribute to unstable quality of silicon carbide semiconductor devices as well as reduction in manufacturing yields thereof.